The invention relates to technology for designing and verifying an electronic design, such as the design of an integrated circuit (“IC”). Modern electronic design is typically performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language (HDL). Common examples of HDLs include Verilog and VHDL. An EDA system typically receives the high level behavioral descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction. Essentially, the process to implement an electronic device begins with functional design and verification (e.g., using RTL), and then proceeds to physical design and verification.
Circuit designers and verification engineers use different methods to verify circuit designs. One common method of verification is the use of simulation. Simulation dynamically verifies a design by monitoring behaviors of the design with respect to test stimuli. For many types of designs, simulation can and should be performed during the design process to ensure that the ultimate goals are achievable and will be realized by the finished product. The exploding demand for high performance electronic products has increased interest in efficient and accurate simulation techniques for integrated circuits. For analog designs, an analog-based simulation approach such as SPICE or SPICE-like simulations (e.g., FastSPICE, HSPICE, PSPICE, or any other SPICE-based or SPICE-compatible simulations) are commonly used to implement simulation of the design. For digital circuit, equivalent digital simulation is performed.
There are many types of electrical analyses that need to be performed to ensure the proper operation of an electronic design. For example, it is often desirable to analyze power distribution networks to check for potential problems relating to IR drops and/or electro-migration effects. Power distribution networks are used to distribute power and ground voltages from pad/package locations to circuit blocks in a design. With continuously shrinking device dimensions, faster switching frequencies and increasing power consumption in deep submicron technologies can cause large switching currents to flow in the power and ground networks, which degrade performance and reliability.
Due to the resistance of interconnects in the power networks, there is a voltage drop across the network, commonly referred to as IR drop. IR drop is a reduction in voltage that occurs on a power net (e.g., a VDD net) in integrated circuits. IC designs usually assume the availability of an ideal power supply that can instantly deliver any amount of current to maintain the specified voltage throughout the chip. In reality, however, a combination of increasing current per-unit area on the die and narrower metal line widths (which causes an increase in the power-grid resistance) causes localized voltage drops within the power grid, leading to decreased power supply voltage at cells and transistors. These localized drops in the power supply voltage decrease the local operating voltage of the chip, potentially causing timing problems and functional failures. IR drop may be both a local and global phenomena. IR drop can be local phenomenon when a number of cells in close proximity switch simultaneously, causing IR drop in that localized area. A higher power grid resistance to a specific portion of the chip can also cause localized IR drop. IR drop can be a global phenomenon when activity in one region of a chip causes effects in other regions. For example, one logic block may suffer from IR drop because of the current drawn by another nearby logic block.
The recent advances in very deep sub-micron (VDSM) integrated circuits (ICs) have brought new challenges in the physical design methodology process of integrated systems. In modern electronic circuits, geometries become smaller; clock frequencies increase; and on-chip interconnections gain increased importance in the prediction of performance. Nonetheless, it has been found that from 0.13 μm and bellow, ICs are more susceptible to wear-out over time (electro-migration or EM), which requires some degree of built-in fault-tolerance and a careful design planning. Meanwhile, increased power demanded on ever shrunk chip size causes higher current densities within the power routing. High currents also induce EM effects in which metal lines begin to wear out during a chip's lifetime. Electro-migration (EM) is an effect on a circuit caused by movement of ions in a conductor structure, which over time will reduce the effective ability and reliability of the conductor to conduct current from one part of the circuit to another. Electro-migration could significantly decrease the reliability of an IC, resulting in possible errors and failures in the IC product. With modern reductions in feature sizes made possible by improving manufacturing processes, the probability of failure due to electro-migration becomes much more possible due to increases of both the power density and the current density of wiring and power structures.
Therefore, it is important for an EDA verification tool to properly and adequately be able to perform electrical analysis to check for potential IR drop and EM problems.